Receiver Pipeline
The receiver demodulates and decodes CDMA2000 reverse link signals in real time through a pipelined processing chain.
The SDR reader preserves the sample timeline across recoverable receive overflows by zero-filling the missed span after a prior hardware timestamp is known. This keeps downstream PCG framing and timestamp-based processing aligned instead of aborting the receiver on a transient overflow.
Pipeline
| Stage | Operation | Details |
|---|---|---|
| 1 | IQ Input | Complex samples at 1.2288 Msps, batched per PCG (1536 chips) |
| 2 | Pilot Search | FFT-based PN correlation, finds active mobiles + timing offsets |
| 3 | Frame Alignment | Gardner TED for fine timing recovery (20 ms / 16 PCGs) |
| 4 | Walsh Despread | RC1: 64-ary Walsh demod. RC3: channelized despread |
| 5 | RAKE | Multi-finger pipelined receiver, FFT + fast-path despread · MRC planned |
| 6 | Deinterleave | Reverse convolutional interleaving, full 20 ms frame |
| 7 | Viterbi Decode | Soft-decision, RC1: R=1/2 K=9, RC3: R=1/4 K=9 |
| 8 | CRC Check | Frame quality indication, feeds FER tracking |
| 9 | L2/L3 Output | Validated frames to MAC/LAC for ARQ and BSC delivery |
Power Control Integration
| Signal | Feeds | Rate |
|---|---|---|
| Per-PCG Eb/Nt | Reverse inner loop (sigma-delta → PCB) | 800 Hz |
| Frame CRC pass/fail | Reverse outer loop (FER → target Eb/Nt) | Per frame |
| PCB output | Forward traffic channel (punctured into TX) | 800 Hz |